With a plesiochronous communication method, in particular during S(H)DSL transmission, data symbols are combined and transmitted in frames, whereby the length of the frames is changed in relation to a reference length by injecting or omitting stuffing data symbols in such a way that the frame length or clock of the frame transmission averaged over several frames is synchronous with a data clock. The data symbols within the frames are therefore transmitted at a constant symbol frequency. In this way it is possible to transmit data symbols, which are provided for transmission in a data source clock, at the symbol frequency and on a receiving side to again insert these into the data source frequency. This is important in particular if a data source frequency, which is also variable under certain circumstances, is the case but data symbols nevertheless must still be transmitted at a constant symbol frequency, in order to achieve transmission tuned to the constant electrical characteristics in particular of a wire-bound transmission channel. The data clock is a measure for the frequency, at which the data symbols to be transmitted arise, or the data source frequency. Since several data symbols are transmitted in a frame, the frame frequency is necessarily substantially lower than the data source frequency. The data clock is therefore advantageously scaled, the data source frequency usually being divided by the number of data symbols and stuffing data elements normally transmitted in a frame, in order to obtain a signal corresponding to the frame transmission.
This injection or omission of stuffing data symbols within the frames is also known as stuffing. During an S(H)DSL transmission for example the standard length of a frame is 6 ms. Irrespective of the data symbols of fixed length waiting to be transmitted the length of the frames will be controlled by means of the stuffing data symbols in such a manner that this on average deviates slightly from the standard length.
The frames 1 shown in FIG. 4 have varying lengths, which have been produced by injected stuffing data symbols, whereby the data symbols 2 have been expanded by the stuffing data symbols 2a and for example the frame 1 shown on the right has four data symbols 2 and the frame 1 shown on the left next to it has four data symbols 2 and a stuffing data symbol 2a and therefore in total five data symbols or stuffing data symbols. FIG. 4 shows the structure of frames 1, which are transmitted one after the other and in each case exhibit data symbols 2. A known device for controlling the frame length is shown in FIG. 5. The device comprises a phase detector 3, to which on the input side a data clock pulse 6 and the signal of the frame transmission 7 are sent. The phase detector 3 dependent on the phase difference between the two input signals produces an adjusting signal 5, with which a frame generator 4 is controlled. The frame generator 4 receives a data source frequency via a signal with the data symbols to be transmitted, not illustrated, and is set up in such a manner that it emits these data symbols in the clock of a symbol frequency, which is supplied via a symbol frequency line 8 and within a frame, the length of which is adjusted by the signal 5. The phase detector 3 is also connected to the symbol frequency line 8 and thereby receives the symbol frequency. The phase detector 3 is set up in such a manner that to determine the phase difference between the two input signals it computes in which periods of the symbol frequency an edge of the data clock pulse 6 or the beginning of a new frame within the frame transmission signal 7 falls and by comparing the duration of the periods concerned of the symbol frequency signal determines the phase difference. The frame transmission signal 7 is transmitted wire-bound to a receiver, which by means of a known clock and data recovery device, extracts from the frame transmission signal 7 both the data symbols and the symbol frequency. A device is shown in FIG. 6, with which the data source frequency is recovered on the receiving side dependent on the symbol frequency, that is transmitted via a symbol frequency line 8, and the frame transmission signal 7 or the frame transmission 7. For this purpose the device has a deframer 9, which analyzes the data symbols in the frame transmission signal 7, extracts the frame structure and sends a signal synchronous with the frame to a PLL circuit. The PLL circuit consists of a phase detector 10, the output signal of which is filtered through a loop filter 11 with a proportional and an integral section and fed to a controlled oscillator 12. The output signal of the oscillator 12 is divided by a divisor 13 and fed back to an input of the phase detector 10. The factor of the divisor 13 is arranged so that the output signal of the oscillator 12 corresponds to the data source frequency. The data symbols contained in the frame transmission signal 7 are passed to the receiving side at the data source frequency.
If on the sending side the data source frequency is exactly synchronous to the symbol frequency or to the symbol frequency adapted to the amount of data symbols transmitted in a frame 1, stuffing data symbols are injected or omitted alternating into the frames 1. Therefore the structure with alternating lengths for the frames 1, shown in FIG. 4, results for the frames 1. The average frame length corresponds in this case exactly to the standard length of the frame length, for example 6 ms with S(H)DSL. If the data clock however is not exactly synchronous to the symbol frequency or the divided symbol frequency, the frame length is not always alternating, but after a certain amount of frames stuffing data symbols are injected or omitted several times one after the other, in order to compensate the slight deviation or to adjust the average frame length to the data clock.
In FIG. 7 such a case is shown, whereby the progression 14 corresponds to the phase of the frame transmission signal 7 and the progression 15 to the phase of the data clock on the data clock line 6. The phase of the frame transmission corresponds thereby to the time situation of the changes between the frames. From this progression it can be seen that the phase 14 of the frame transmission 7 as a result of the alternating injection or omission of a stuffing data symbol constantly jumps to and fro, but on average remains constant for a certain number of frames. However as soon as the difference between the phase 15 and the data clock 6 and the average phase of the phase progression 14 becomes too great, a stuffing data symbol is injected twice one after the other into a frame 1, whereupon again the strictly alternating injection or omission of the stuffing data symbol begins. In the case illustrated after 13 standard cycles with alternating stuffing every time, stuffing data symbols are injected twice after each other, so that a step-like structure of the zigzag progression 14 results.
In FIG. 7 the phase of the data clock 6 generated on the receiving side by the PLL circuit is shown under the progression 14 with the progression 16. An interruption of the alternating stuffing on the sending side by injecting or omitting stuffing data symbols several times one after the other leads on the receiving side in the phase of the recovered data clock to timing jitter, which is all the more difficult to suppress the greater the time interval between them. The reason for this is that with a long time interval the frequency, at which jitter arises, decreases and can be suppressed with all the more difficulty by the PLL on the receiving side. This means that the disadvantageous jitter on the receiving side is all the more pronounced, the greater the number of frames, with which strictly alternating stuffing data are injected and omitted or the lesser the deviation of the data source frequency from the symbol frequency or the adapted symbol frequency.